To ease supply-chain pressures, NVIDIA has quietly lowered the HBM4 bandwidth target and downgraded its 12-layer stack to an 8-layer hybrid configuration. This "dimension-reduction" move aims to significantly cut costs while effectively lowering the threshold for suppliers, potentially breaking the bottleneck in HBM production capacity.
$NVIDIA (NVDA.US)$It is undertaking a major overhaul of the memory architecture for its next-generation AI accelerator platform, with two parallel strategic threads—downgrading stack specifications and revising bandwidth targets—reflecting deep-seated supply-chain pressures and cost‑optimization imperatives in the high-bandwidth memory segment.
According to ZDNet, Samsung and SK Hynix are preparing to supply NVIDIA's Rubin Ultra with 8-layer HBM4 in the second quarter of 2027, a move that could alter the original plan to adopt 12-layer HBM4E. Meanwhile, as reported by Wccftech, NVIDIA quietly reduced the HBM4 bandwidth specifications for its Vera Rubin platform as early as last September—cutting the bandwidth per Rubin GPU by about 13%, with the reduction reaching as high as 26% at the HGX Rubin NVL8 system level.
The aforementioned adjustments directly affect both HBM suppliers and the GPU industry chain. The lowered bandwidth threshold means that more HBM4 products are likely to pass NVIDIA's qualification, expanding potential supply sources; meanwhile, the introduction of an 8-layer configuration will reduce the cost and bill-of-materials burden per HBM stack, which, against the backdrop of persistently tight HBM supply, is expected to help alleviate capacity bottlenecks.
Rubin Ultra has abandoned the 12-layer design in favor of an 8-layer HBM4 hybrid configuration.
According to ZDNet, 8-layer HBM4 was not originally part of NVIDIA's plans, but as the company revisited the memory configuration for the Rubin Ultra, related discussions gained momentum in the third quarter of 2026. The report notes that the Rubin Ultra was initially slated to rely on 12-layer HBM4E, but the final product may instead adopt a hybrid solution combining 8-layer HBM4 with HBM4E, in order to mitigate supply constraints arising from thermal management challenges and lower yield rates associated with 12-layer stacking.
ZDNet, citing sources familiar with the matter, reports that NVIDIA is expected to deploy both 8-layer HBM4 and 8-layer HBM4E in its NVL rack-level systems based on Rubin Ultra, depending on the rack configuration. Notably, although both Samsung and SK Hynix have completed NVIDIA's qualification for 12-layer HBM4, their 8-layer products still require separate certification procedures.
TrendForce analysis indicates that, compared with 12-layer HBM modules, the 8-layer configuration uses fewer DRAM chips, thereby reducing both the per‑stack cost and the overall bill of materials for GPUs, while also enabling a given HBM bit width to support more GPUs. Given the ongoing tightness in HBM supply, the 8-layer solution is expected to become the preferred option under evaluation for many GPU and ASIC manufacturers by 2027.
ZDNet also reported that while 12-layer HBM4 will remain the mainstream configuration in 2026, the adoption rate of 8-layer HBM4 is expected to surge starting from mid-2027. This trend may extend beyond NVIDIA—according to an analysis cited by Economy Tribune, Anthropic's self-developed AI chip could also utilize 8-layer HBM4, with Samsung potentially taking on both the foundry services and memory supply for this project.
Bandwidth metrics have been quietly revised downward, and the pool of eligible suppliers is expected to expand.
Regarding bandwidth specification adjustments, according to a report by Wccftech, the archived version of NVIDIA's official specifications page dated September 1 shows that the Vera Rubin NVL72 system is equipped with 20.7 TB of HBM4 capacity and 1,580 TB/s of bandwidth, while the Vera Rubin superchip has 576 GB of capacity per core and 44 TB/s of bandwidth, with each Rubin GPU corresponding to 288 GB and 22 TB/s.
Subsequently, NVIDIA quietly lowered its specifications: the HBM4 bandwidth per GPU was reduced from 22 TB/s to 19.2 TB/s, and the NVLink 6 throughput dropped from 3.6 TB/s to 3 TB/s, representing reductions of approximately 13% and 17%, respectively. According to IT Home, the memory specification of the Vera CPU was also adjusted from a fixed 1.5 TB LPDDR5X per chip to "up to 1.5 TB."
Economy Tribune noted that the three major memory manufacturers have now disclosed HBM4 performance data: Samsung and SK Hynix report an HBM4 data transfer rate of 11.7 Gbps per pin (with Samsung reaching up to 13 Gbps), while Micron exceeds 11 Gbps, corresponding to HBM4 stack bandwidths of approximately 3.0 TB/s for Samsung and SK Hynix, and over 2.8 TB/s for Micron.
With each Rubin GPU integrating eight 36 GB HBM4 stacks, achieving the original 22 TB/s bandwidth would require approximately 10.7 Gbps per pin, whereas the revised 19.2 TB/s target corresponds to a pin rate of about 9.4 Gbps. According to an analysis by Economy Tribune, in theory, the performance data already disclosed by memory manufacturers is sufficient to meet NVIDIA's original target; IT Home further notes that, with reduced bandwidth requirements, more HBM4 products are likely to obtain Rubin GPU certification, potentially boosting overall production output.
Editor/Deng