Tao's Law faces its first major test in September.

On the afternoon of May 25, at the IEEE ISCAS 2026 conference in Shanghai, He Tingbo, President of Huawei’s Semiconductor Business Unit, delivered a keynote speech titled 'Exploration and Practice of New Semiconductor Pathways,' formally unveiling the 'Tao (τ) Law'—a strategy that substitutes geometric scaling with time-based miniaturization, employing LogicFolding to compress signal propagation latency, with the goal of achieving transistor density equivalent to a 1.4nm process node by 2031. Her closing remark was: 'The future must belong to open collaboration. Under the Tao Law pathway, we look forward to working closely with scientists, engineers, and industry partners worldwide.'

Seven years after writing, 'Today marks the most heroic Long March in the history of technology,' He Tingbo now presents a different posture.

The A-share market reacted immediately—the STAR 50 Index rose 5.47%, SMIC surged as much as 18% intraday, and nearly 60 semiconductor-related stocks either hit their daily trading limits or gained more than 10%.

Yet on the same day, seven semiconductor companies listed on the A-share market simultaneously announced shareholder sell-downs, including Zhongwei Company (RMB 6 billion) and Montage Technology (RMB 3.324 billion), totaling approximately RMB 12.7 billion in realized gains. A quieter signal emerged from ETF flows—Harvest STAR Chip ETF recorded net outflows of RMB 3.196 billion that day, bringing its year-to-date cumulative net outflows above RMB 12.3 billion; Guolianan Semiconductor ETF saw single-day net outflows of RMB 1.635 billion.

Retail investors are buying, institutions are selling, industrial capital is cashing out, and the index is rising. The coexistence of these two signals itself reflects market indecision.

What the Tao Law Is—and What It Is Not

Stripping away the buzzwords, the Tao Law boils down to one core idea: using 'dual-layer logic folding' at the circuit design level to reduce the RC time constant (τ) of signal propagation, thereby increasing transistor density by one generation within the same process node.

LogicFolding is neither Taiwan Semiconductor’s SoIC nor Intel’s Foveros—both of those involve package-level vertical stacking of pre-fabricated silicon dies. LogicFolding, by contrast, reorganizes logic layers and rewires interconnects within a single die to shorten critical paths. It does not require EUV or High-NA lithography and can theoretically run on existing fabrication processes—this is its key selling point and the fundamental reason it has become a catalyst for today’s A-share semiconductor rally.

Moore's Law is considered a law because Gordon Moore provided a clear mathematical function—transistor density doubles every 18–24 months. Tao's Law has not yet been accompanied by such a publicly disclosed function. As of May 25, after extensive searches by both Chinese and international media, no outlet has obtained the IEEE ISCAS paper PDF or an official Huawei whitepaper. All existing references remain at the conceptual level—the specific scaling function for τ scaling and computable metrics for multi-level co-optimization are currently absent from public materials. This does not necessarily undermine its internal coherence as an industrial framework, but the portion currently accessible to the market is indeed limited.

Overseas reactions have generally been restrained. Bloomberg framed this development as an attempt to 'narrow the gap with Taiwan Semiconductor,' while Reuters and CNBC both included the standard qualifier 'amid U.S. sanctions.' On the night of the announcement, Triolo, Director of Technology Policy at DGA Group, offered a footnote worth reading alongside these reports—he acknowledged that folding/stacking designs can deliver genuine density gains, but also cautioned: 'This package still hasn't addressed the full suite of challenges involved in 1.4nm-class manufacturing—yield, power consumption, thermal management, and device performance.'

This is currently the most restrained—and most specific—caution offered by international observers.

Narrative until September

The window during which Tao's Law can genuinely be priced into markets opens this fall.

In her speech, He Tingbo gave a specific timeline commitment: the next-generation Kirin smartphone chip, launching in autumn 2026, will debut the full LogicFolding dual-layer design. Huawei Central and IT Home received three leaked figures: a 53.5% increase in transistor density, reaching 238 MTr/mm²; a 41% improvement in P-core energy efficiency; and a peak frequency of 3.1 GHz. Based on Huawei’s flagship release cadence, this chip will most likely power the Mate 90 series.

Placing these figures back onto the 2026 SoC landscape reveals another layer of meaning.

238 MTr/mm² roughly corresponds to$Taiwan Semiconductor (TSM.US)$ the high-density logic library of the N3E node (approximately 215–220 MTr/mm²), slightly better; yet it still lags behind the high-density library of the N2 node (measured at approximately 313 MTr/mm²). In other words, Tao's Law, as realized in 2026, aligns with the 3nm high-density tier, still a full five-year roadmap away from the 1.4nm target shown in presentations. There is nothing shameful about this starting point—it demonstrates that the first generation of LogicFolding is a serious engineering product—but it also means pricing the autumn Mate 90 directly against a 1.4nm benchmark would be misaligned.

The figure of 3.1 GHz must also be viewed within the context of flagship SoC clock speeds expected in 2026—Apple’s A18 Pro and Qualcomm’s Snapdragon 8 Gen 4 are both projected to exceed 4.0 GHz in peak frequency. The gap is objectively real and will be immediately quantified in benchmark comparisons. How one interprets this number depends on whether 'system-level energy efficiency' is prioritized over—or under—'peak clock frequency.'

A useful point of comparison—before the official launch of the Kirin 9020 last year, Huawei’s pre-release disclosure claimed it would 'outperform the Snapdragon 8+ Gen 1.' Subsequent real-world testing by Notebookcheck showed its single-core performance still lagged approximately 30% behind the Snapdragon 8 Gen 3, with a die area 15% larger than that of the Kirin 9010. This comparison does not prove that the Kirin 2026 will follow the same trajectory, but it will lead the market to apply a certain discount to official teasers before September.

The day the Mate 90 launched marked the first public milestone of a five-year roadmap. Prior to that, judgments such as 'Tao's Law reshaping the landscape' were primarily based on He Tingbo’s speech and Huawei’s disclosed specifications—a phase fairly described as 'awaiting hard data.'

Within the 381 chip designs, two key points stand out.

Another figure from the launch event that sparked significant social media sharing was: '381 chip designs have been mass-produced over the past six years.' This is a substantial number—it indeed demonstrates that Huawei’s semiconductor team has maintained a large-scale engineering organization capable of consistently delivering chips despite constraints.

However, the 381 designs warrant closer segmentation. Over the past six years, Huawei has publicly released fewer than 10 consumer-grade Kirin SKUs—including the 9000S, 9010, and 9020. The Ascend AI series comprises roughly 5–8 models, Kunpeng server chips 3–5, Balong baseband chips 3–5, and Tiangang base station chips another 3–5. The remaining 350+ designs consist largely of mature-node chips at 28nm and above, spanning automotive, Wi-Fi, PMICs, display drivers, IoT, and other categories.

This is not meant to diminish the significance of the 381 figure—Huawei’s ability to sustain a comprehensive product portfolio covering communications, AI, automotive, consumer electronics, and industrial applications using restricted manufacturing processes is a remarkable achievement. It reflects the depth of its engineering organization and should be viewed separately from 'progress in advanced process breakthroughs.' Currently, the market tends to treat it as indirect evidence of the latter—an interpretation that may warrant some temporary discounting.

Switching to a different curve

According to Huawei’s stated 2031 roadmap endpoint—equivalent to a 1.4nm node, with P-cores running at 5.0GHz and transistor density exceeding 400 million transistors per square millimeter (MTr/mm²).

Placing this timeline within the context of global advanced process roadmaps yields a more complete picture.$Taiwan Semiconductor (TSM.US)$The 1nm node (A10), per publicly available roadmaps, is scheduled for mass production in 2030, supporting 200 billion to 1 trillion transistors per die; the A14 (1.4nm) node is planned to enter high-volume manufacturing (HVM) in 2028.$Intel (INTC.US)$The 14A tool has already completed acceptance testing of the ASML TWINSCAN EXE:5200B High-NA EUV system in 2026, with the goal of entering high-volume manufacturing (HVM) in early 2027.

Aligning these two curves—by 2031, when Huawei achieves an equivalent of 1.4nm, Taiwan Semiconductor will have reached the 1nm/A10 node, and Intel may already be at its 10A/8A nodes. The absolute process-node gap, currently around three generations, will still stand at two to three generations by 2031.

However, this alignment method itself is ambiguous. Taiwan Semiconductor’s curve follows geometric scaling, whereas Tao’s Law opts for temporal scaling—prioritizing density and energy efficiency achievable within the same node as optimization targets. Under sanctions, chasing absolute parity along Moore’s Law offers little visibility of an endpoint; switching to a different curve—prioritizing 'user-experience gap' over 'absolute process-node gap'—represents an engineering-justifiable and industrially pragmatic second-best choice.

Consequently, the nature of the generational gap has changed. It has shifted from the historical pattern of 'being several generations apart on the same curve' to 'a distance between two curves across different dimensions.' Tao’s Law won’t eliminate the numerical gap, but it may reduce the perceptible impact of that gap on end-user products. This is its real bet—and the promise it must deliver through products after September.

What Was Rushed, and What Wasn’t

What exactly was priced into the +5.47% gain in the STAR 50 Index on May 25?

Listing the concurrent catalysts that day clarifies the picture. ChangXin Memory Technologies’ IPO review meeting was scheduled for May 27, seeking to raise RMB 29.5 billion—a development widely viewed by the market as one of the most significant marginal events for the memory supply chain. Anticipated progress on a U.S.-Iran agreement continued to bolster global risk appetite—the Nikkei 225 breached 65,000 for the first time that day. Separate positive momentum came from reports of Korean memory makers raising prices. That evening, Hygon Information and Sugon announced a share-swap merger plan, while Sigmastar surged by 20%, temporarily shifting capital focus from 'concept-driven plays' to 'restructuring themes.'

Viewed collectively, Tao’s Law acted more as an amplifier of the day’s narrative, while the primary pricing drivers were dispersed among parallel catalysts: ChangXin’s IPO, U.S.-Iran expectations, memory price hikes, and the Hygon-Sugon merger. Attributing the entire 5.47% move solely to a single 'chip law' would skew subsequent asset assessments.

Yet this narrative amplifier has directionality—it magnifies sentiment premiums on the design side. Will Semiconductor has already risen 50% over the past month, with capital flowing into Cambricon, Maxscend, and Unigroup Guoxin. These assets exhibit the weakest engineering dependence on LogicFolding—they benefit primarily from renewed confidence in the broader domestic semiconductor sector, with little direct linkage to which specific process node 'dual-layer logic folding' ultimately lands on.

The true ranking of engineering dependencies should look like this—

Packaging + Equipment > Materials > Design

The packaging segment is the first gateway for the physical implementation of LogicFolding. Dual-layer logic folding creates rigid demand for high-density bonding, TSVs, and hybrid bonding—JCET’s XDFOI technology has already entered mass production, and Tongfu Microelectronics’ 5nm chiplet solution is also in mass production, with advanced packaging accounting for more than half of both companies’ revenues. This segment represents the true core.

The equipment segment follows closely behind. Multi-level co-optimization imposes comprehensive requirements on etch aspect ratios, film uniformity, CMP planarity, bonding alignment, and high-speed testing. Key players include NAURA, Advanced Micro-Fabrication Equipment (AMEC), Piotech, Hwatsing Technology, Changchuan Technology, and Jingce Electronic. Among them, Piotech’s hybrid bonding tools and Changchuan’s high-speed testers are two segments that the market has not yet fully priced in. Once LogicFolding is truly implemented at scale, bonding process usage will double, and test equipment will require synchronous upgrades in frequency and channel count—a transmission chain that research reports and sell-side analysts have barely addressed to date.

The materials segment trails slightly further behind. Dinglong Shares’ CMP polishing pads and Anji Microelectronics’ slurries will see doubled consumption under multi-layer stacking scenarios, but their monetization timeline lags behind equipment by roughly half a cycle.

The design segment was the hottest on the day and also the one with the shallowest engineering dependency. The recent share price gains of Will Semiconductor, Cambricon, and Unigroup Guoxin contain minimal direct exposure to LogicFolding benefits—most of the upside stems from sentiment spillover driven by a broader recovery in the domestic semiconductor ecosystem. Sentiment-driven rallies may persist until September; post-September performance will hinge on earnings validation—making this segment the most vulnerable to valuation corrections.

In the Hong Kong stock market,$SMIC (00981.HK)$It is the core enabler of LogicFolding’s mass-production processes, corresponding to an intraday gain of over 18% in its A-share listing;$HUA HONG SEMI (01347.HK)$Absorbing overflow orders from mature-node foundries. Overseas,$Taiwan Semiconductor (TSM.US)$、$Intel (INTC.US)$、$Samsung Electronics (005930.KR)$、$ASML Holding (ASML.US)$As of pre-market hours in the U.S. on the day, there was no official response—which in itself is not indicative of any stance, as formal comments typically await the next earnings call or technical forum. The market will get its first opportunity for international benchmarking after foreign brokerage reports begin rolling out on May 26.

What triggers it, and what breaks it

Each asset tier has its own trigger conditions and failure conditions—listed below tier by tier.

Trigger condition for the packaging chain: Kirin’s fall 2026 real-world test validates the leaked density of 238 MTr/mm², coupled with >30% sequential order growth in H2 for JCET and Tongfu. Failure condition: Kirin’s actual PPA metrics fall short of expectations, or yield issues delay shipment schedules.

Trigger condition for the equipment chain: SMIC/Hua Hong further increases capital expenditure in H2 2026, and domestic content ratio exceeds 50%. Failure condition: Continued expansion of share sell-offs (RMB 12.7 billion in sell-off announcements as of May 25), and Phase III of China Integrated Circuit Industry Investment Fund (Big Fund III) deployment lags behind expectations.

Trigger condition for testing equipment: Changchuan and Huafeng fulfill H2 orders, and domestic substitution of high-speed ATE accelerates. Failure condition: Overseas test equipment supply becomes readily available again, weakening the domestic substitution thesis.

Trigger condition for EDA STCO: Huada Empyrean and Primarius secure orders related to the LogicFolding toolchain. Failure condition: Overseas EDA vendors (Synopsys, Cadence) are granted relief from restrictions and continue to dominate the advanced design market.

The only hard inflection point—the real-world performance data from the September Mate 90 series launch. Until then, all price movements reflect sentiment-driven volatility; afterward, the market enters a phase of earnings validation, with extreme divergence expected.

Risks—and why September is the most critical month

Scenarios in which Tao’s Law could fail must be assessed within specific time windows.

The most immediate risk over the next 1–3 months is the broadening of the sell-off trend and sell-side report recalibrations. As of May 25, RMB 12.7 billion in sell-off announcements have been made, alongside RMB 12.3 billion in net outflows from institutional ETFs—if significant new sell-offs occur around ChangXin’s listing review on May 27, or if foreign institutions issue materially revised reports at Monday’s market open, the window for narrative-driven positioning may close sooner than expected.

The key risk over the medium term (3–12 months) lies in the Mate 90 real-world test results. Siemens EDA highlighted several hard constraints of 3D IC technology in two academic white papers published in early 2026—namely, elevated local heat flux density, a physical stacking limit of 6–8 layers, and interconnect cracking/delamination impacting long-term reliability. Smartphone SoCs represent one of the most challenging applications for 3D stacking due to high transient power consumption and limited thermal dissipation space. If the Mate 90 underperforms significantly in thermal management or benchmark scores relative to leaks, the 'path reinvention' narrative will face its first major reality check.

The long-term (1–5 year) risk stems from external factors—the biggest overhanging threat is whether the U.S. Bureau of Industry and Security (BIS) adds 'LogicFolding/3D stacking' process equipment and EDA services to its next round of export controls.

Key signals to monitor next

Short-term signals to monitor—

After the market opens on May 26, whether capital flows into the STAR Market semiconductor sector continue to front-run or show clear profit-taking. Pay close attention to high-frequency price-volume dynamics and northbound capital movements for SMIC, JCET Group, and Tongfu Microelectronics.

The listing review outcome for Changxin Technology on May 27. If approved, sentiment across the memory supply chain will reignite, indirectly validating the dual narrative of Tao’s Law and domestic memory development; if unexpectedly rejected, the entire memory + AI computing power chain will experience a synchronized pullback.

Around May 28, whether dedicated research reports from major foreign institutions such as Morgan Stanley, Goldman Sachs, and UBS Group are released. Sell-side analysts overseas remained silent on May 25, and this silence is expected to break after Tuesday.

Medium-term focus:$SMIC (00981.HK)$Q2 earnings call commentary—whether management explicitly addresses the production ramp-up timeline implied by Tao’s Law.

Long-term, there is only one signal—the benchmark scores, battery life, thermal performance, and camera real-world tests on the launch day of the Mate 90 series in September. This will serve as the first engineering proof of concept (PoC) for the five-year roadmap.

What we’re waiting for is not the law itself, but pricing

Tao’s Law should not be interpreted as a triumphant declaration that 'China’s semiconductor industry has bypassed Moore’s Law,' nor as a reactive contingency plan under sanctions pressure. Rather, it resembles a carefully crafted engineering framework—one that acknowledges the persistent gap along the Moore’s Law curve cannot be quickly closed, and instead seeks to narrow the user experience gap through system-level optimization. This approach represents a sound engineering choice and a rational industrial strategy. Whether the market will price it accordingly is another matter entirely.

The 5.47% gain prior to September was largely driven by narrative—narratives can boost sentiment, amplify concepts, and extend the rally for design-side stocks. However, 12.7 billion in industrial capital divestments and 12.3 billion in net ETF outflows indicate that those seriously pricing the asset prefer to wait until September.

The real-world test results unveiled on the day of the Mate 90 launch will determine whether Tao’s Law is interpreted as 'a new methodology for China’s semiconductor industry' or relegated once again to an industrial framework awaiting validation in the next cycle. Neither outcome represents a final conclusion—Tao’s Law is a five-year plan, and May 25 merely marks the establishment of its first milestone.

By that date, the market’s most fundamentally valuable assets won’t be design-side firms like Will Semiconductor and Cambricon—but rather packaging leaders such as JCET and Tongfu Microelectronics; equipment suppliers like PIOTECH and Changchuan Technology, which the market has overlooked; and Huada Empyrean’s yet-to-be-fully-priced EDA STCO long-term revaluation trajectory. The sequence outlined here will clarify itself through execution rhythms after September.

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Editor/melody