Taiwan Semiconductor has disclosed for the first time the results of joint validation with Ibiden and Innolux on integrating glass substrates into its CoWoS advanced packaging technology. Data show that glass substrates can reduce package warpage by 16%, lower the coefficient of thermal expansion by 19%, increase elastic modulus by 31%, and decrease power delivery resistance and inductance by 27% and 42%, respectively. Taiwan Semiconductor also revealed that packaging competition is shifting from CoWoS to CoPoS, marking the official start of the industrial validation phase for glass substrates.
AI chips are growing larger, and the performance ceiling of packaging materials is being redefined.
According to a Digitimes report on June 16, Taiwan Semiconductor recently disclosed for the first time progress on the application of 'glass substrate' technology, confirming collaboration with ABF substrate manufacturer Ibiden and panel maker Innolux to jointly validate the feasibility of integrating glass substrates into next-generation CoWoS advanced packaging.
Meanwhile, Taiwan Semiconductor also revealed that competition in advanced packaging is gradually shifting from CoWoS to the CoPoS (Chip-on-Panel-on-Substrate) arena, and it has begun proactively building a complete ecosystem. Industry sources noted that rapidly intensifying pressure—from customer demands for technical specifications and capacity, as well as from competitors such as Intel and Samsung—has compelled Taiwan Semiconductor, traditionally known for its cautious and non-aggressive approach, to accelerate its pace of technology adoption.
Data speaks: Performance advantages of glass substrates in large-scale packaging
The test samples used by Taiwan Semiconductor featured a 0.8mm glass core substrate, with a packaging specification of 5x Reticle CoW, resulting in an overall package size of 85×110mm—placing it in the category of large AI GPU packages.
Validation results showed clear improvements across multiple key metrics compared to organic substrates:
16% improvement in package warpage (COP): Package flatness directly affects yield. As AI GPU dimensions continue to expand (e.g., NVIDIA’s GB200, GB300, and the Rubin platform now entering mass production), warpage control has become increasingly critical.
19% reduction in effective coefficient of thermal expansion (Effective CTE): The CTE of glass more closely matches that of silicon chips, resulting in lower thermal stress during temperature fluctuations and helping to reduce cracks and solder joint fatigue.
31% increase in effective elastic modulus (Effective Modulus): The higher rigidity of the substrate is crucial for supporting large packages with ever-increasing HBM stack heights.
Power delivery integrity: Resistance reduced by 27% and inductance reduced by 42%, significantly enhancing power delivery efficiency.
Taiwan Semiconductor specifically emphasized that 'no severe warpage or delamination' (No SeWaRe & Delamination) was observed during testing—two issues historically known as major yield killers in large-scale packaging.
“Thinner but better”: Glass substrates pose a direct challenge to organic substrates
In this validation, Taiwan Semiconductor directly provided a qualitative comparison between the two substrate types: Glass-SBT achieves 'thinner but better COP,' whereas Organic-SBT results in 'thicker but worse COP.'
In other words, glass substrates can not only be made thinner but also offer superior package flatness and reliability. This conclusion carries direct implications for technological substitution in the AI chip market, where high-density and large-form-factor packaging are critical.
However, Taiwan Semiconductor also clearly stated that further research is still needed on glass thickness optimization and large-scale CoWoS packaging layouts, indicating that mass production remains some distance away.
The hardest part isn’t the glass itself—it’s drilling the vias
The core technical challenge of glass substrates lies in Through Glass Vias (TGVs).
Glass is inherently an insulator; therefore, tens of thousands of TGVs must be created to establish vertical conductive pathways for signal and power transmission. However, due to its high hardness and brittleness, glass is prone to microcracking during processing, which compromises reliability and yield.
Via formation, copper filling quality, and long-term thermal reliability are regarded as the three critical hurdles that must be overcome before glass substrates can reach mass production.
Supply chain dynamics: Why Ibiden and Innolux have entered the field
The list of collaborators itself also reveals the direction of supply chain positioning.
Ibiden is currently a key substrate supplier for NVIDIA and AMD AI chips. It previously announced a JPY 500 billion investment to expand its new factory in Ono, Gifu Prefecture, focusing specifically on high-end packaging substrates for AI servers. Its inclusion by Taiwan Semiconductor in glass substrate validation cooperation further confirms its central role in the next-generation packaging supply chain.
Innolux’s inclusion is viewed by the industry as a significant step for panel manufacturers entering the glass substrate segment. Panel makers already possess established capabilities in large-size glass processing, and collaboration with Taiwan Semiconductor could open new business avenues for them.
Competitive pressure: Intel and Samsung are already ahead
Taiwan Semiconductor’s current acceleration is driven by clear competitive pressure.
Intel has been active in the glass substrate field for over a decade, making it the earliest and most deeply invested global player. Its pilot glass substrate production line in Arizona, USA, is now gradually transitioning to commercialization, as it seeks to combine glass substrates with ultra-large chiplet packaging to secure orders from AI GPU and ASIC customers.
Samsung Electro-Mechanics (Semco) plans to establish a glass substrate pilot production line in 2025 and has formed a joint venture with Japan’s Sumitomo Chemical Group to proactively build out its glass substrate supply chain.
By comparison, Taiwan Semiconductor is only now publicly disclosing its glass substrate validation results for the first time. While its public timeline lags behind Intel and Samsung, its tripartite validation approach—partnering with Ibiden and Innolux—and its direct integration with CoWoS/CoPoS packaging platforms demonstrate that it is rapidly advancing at its own pace.
Editor/Lambor