Intel has unveiled a patent for XBM memory, replacing HBM silicon interposers with UCIe serial interconnects and a back-end DRAM architecture to reduce packaging costs and enhance bandwidth and density. However, commercialization is not expected until after 2030, making it unlikely to challenge the HBM ecosystem currently dominated by SK Hynix and Samsung in the near term.
Intel is seeking to challenge the dominance of High Bandwidth Memory (HBM) with a novel memory architecture, but its commercialization prospects remain distant.
A patent application published by Intel last week revealed its 'Cross-Batch Memory' (XBM) architecture. This design aims to bypass HBM’s reliance on silicon interposers by replacing conventional DRAM and its ultra-wide interface with back-end-process transistors and serial UCIe interconnects, significantly reducing packaging costs.
According to Wccftech, the target timeline for XBM commercialization is set for post-2030, aligning with the development schedule of the ZAM memory architecture jointly pursued by Intel and SAIMEMORY, a subsidiary of SoftBank.
The HBM market is currently dominated by South Korean manufacturers, and dual pressures of supply shortages and high costs are driving the industry to seek alternatives. Intel’s recent patent disclosure introduces a new variable into this competitive landscape, though analysts note that ecosystem barriers and platform compatibility issues will be major obstacles to XBM’s market adoption.
XBM Architecture: Replacing Wide Parallel Interfaces with Serial UCIe Interconnects
According to the patent, the core of the XBM architecture lies in connecting DRAM modules to UCIe I/O modules operating at 32 GT/s, with I/O signals routed through the base die.
Each XBM stack offers per-die capacities ranging from 0.5 GB to 5 GB. Each sub-channel consists of 12 data modules; an 8-layer XBM stack can accommodate up to 96 data modules, while a 16-layer stack can support up to 192, with channels operating at a frequency of 2 GHz.
In terms of packaging, XBM supports multiple configurations, including Memory-on-Package (MoP), enabling higher bandwidth and capacity within a smaller form factor. This flexibility is viewed as one of XBM’s potential advantages over existing HBM solutions.
Back-End DRAM Process: Enhancing Area Efficiency and TSV Density
XBM’s key process-level innovation lies in its adoption of a 1T1C (one-transistor-one-capacitor) back-end DRAM structure.
According to Wccftech, the approach fabricates transistors in the back-end-of-line (BEOL) metal layers rather than the front-end silicon substrate, significantly improving area efficiency and thereby freeing up more space for through-silicon vias (TSVs), which enables higher memory density and bandwidth.
This design directly addresses a core limitation of existing HBM. As TrendForce cited from Global Economic News analysis, traditional HBM requires micro-bump processes when vertically stacking DRAM chips, resulting in relatively high manufacturing costs; silicon interposers further increase wiring complexity and overall cost. The XBM architecture was specifically proposed to overcome these constraints.
SK Hynix and Samsung's first-mover advantage remains difficult to challenge.
Despite XBM’s technical appeal, its potential to disrupt the current competitive landscape remains questionable.
As noted by Global Economic News, SK Hynix and Samsung Electronics have been deeply investing for several years in cost-reduction technologies such as standard chiplets, UCIe, and fan-out packaging, thereby accumulating significant first-mover advantages in cost optimization.
An even more critical barrier lies at the ecosystem level. Currently, the global AI accelerator ecosystem—centered around NVIDIA—is highly optimized for existing HBM architectures and their wide parallel interfaces. Migration to alternative memory architectures entails substantial platform compatibility and software adaptation costs. This means that even if XBM demonstrates competitive technical specifications, its large-scale commercial adoption must overcome considerable industry inertia.
XBM’s commercialization window is expected to arrive only after 2030, implying that HBM will remain the dominant solution for high-bandwidth memory requirements in AI chips for the foreseeable future. Intel’s patent filing thus represents more of an exploratory step toward a potential technological direction than an immediate disruption to the current market landscape.