Taiwan Semiconductor has completed development verification for its A16 process, with mass production expected in Q4 2026. This process adopts "Super Power Rail" backside power delivery technology, which moves the power distribution network to the rear of the chip, resolving routing bottlenecks and improving power delivery efficiency. The key lies in minimizing changes to front-end structures, thereby reducing customers' design migration costs and providing an advanced, energy-efficient, and highly compatible process solution for AI and high-performance computing chips.
Taiwan Semiconductor achieves another key milestone in advanced process technology.
According to industry sources cited by DigiTimes, a media outlet in the Taiwan region of China, Taiwan Semiconductor has completed the development and validation of its A16 process node and plans to commence mass production in the fourth quarter of this year. As Taiwan Semiconductor’s first angstrom-level CMOS platform utilizing the “Super Power Rail” backside power delivery architecture, the A16 targets applications with stringent requirements for computing power, energy efficiency, and power stability, such as AI and high-performance computing.
Reportedly, compared to the previous N2P process node, the A16 delivers an 8% to 10% performance improvement at the same power consumption, or reduces power consumption by 15% to 20% at the same performance level, while increasing transistor density by 8% to 10%. Its core advantage lies not only in the introduction of backside power delivery but also in minimizing changes to front-side transistor structures and the existing design ecosystem.
Backside Power Delivery Resolves the “Routing Bottleneck” in Advanced Process Nodes
As process nodes continue to shrink, the front side of traditional chips must handle both power delivery and signal interconnection within limited routing space, which is increasingly insufficient to meet the demands of high-performance computing chips. This exacerbates issues such as routing congestion and IR drop (resistive voltage drop).
The concept of backside power delivery involves migrating the power distribution network from the front to the back of the chip, thereby freeing up front-side routing space for signal interconnections and reducing resistance and voltage drop in the power delivery path. However, this technology is not simply a matter of “moving power to the back.” Backside power delivery typically requires adjustments to transistors, standard cells, and even the entire design flow, potentially imposing significant IP restructuring and design migration costs on customers.
Taiwan Semiconductor’s A16 utilizes dedicated vertical backside contacts (VB) to connect power directly to the source and drain of transistors, achieving separation between the power delivery network and the signal network.
More critically, Taiwan Semiconductor aims to minimize modifications to front-side structures. Reportedly, the A16 retains the gate density and NanoFlex design flexibility of the N2P node, enhancing power delivery efficiency while maintaining compatibility with the existing chip design ecosystem as much as possible.
This implies that customers who have already designed based on Taiwan Semiconductor’s advanced processes may not need to extensively restructure standard cells and design architectures when migrating to the A16. This advantage is particularly important for AI accelerators and high-performance computing chips, which involve long design cycles and high IP complexity.
AI Computing Demand Accelerates the Evolution of Advanced Process Nodes
The launch of the A16 reflects the increasingly stringent requirements that AI chips impose on advanced manufacturing processes.
AI accelerators and high-performance computing chips typically integrate a large number of computational units, imposing far higher demands on power integrity, signal routing, and energy efficiency than traditional chips. Backside power delivery can free up front-side routing resources and improve power delivery efficiency, making it a critical technological pathway for further enhancing the performance and energy efficiency of AI chips.
If the A16 enters mass production in the fourth quarter of this year as planned, Taiwan Semiconductor will be the first to accumulate large-scale mass production experience with backside power delivery. As demand for AI computing power continues to grow, whether the A16 can win customer favor through its combined advantages in performance, energy efficiency, and design compatibility will become a key indicator of Taiwan Semiconductor’s competitiveness in advanced manufacturing processes in the next phase.