SEMICON 2026 sends new signals for the semiconductor industry: advanced packaging is upgrading toward 3D system integration, CoWoS capacity continues to expand and spill over to OSATs, CPO is accelerating mass production, while testing and equipment lead times have become new bottlenecks, and the AI ASIC ecosystem is further maturing. UBS Group is bullish on Taiwan Semiconductor's 3DFabric capacity expansion, Citi focuses on CPO manufacturing, and Nomura warns of capacity constraints in testing and equipment segments, as AI-driven capacity expansion accelerates into the backend processes.
As AI computing power continues to expand, the logic behind semiconductor capacity expansion is extending from chips and wafer fabrication to advanced packaging, optical interconnects, and testing. During SEMICON Taiwan 2026, surveys by Citi, Nomura, and UBS Group highlighted six key trends: the upgrade of advanced packaging toward 3D system integration, continued CoWoS capacity expansion with a shift toward OSATs, accelerated mass production of CPO, testing emerging as a new bottleneck, lengthened lead times for critical equipment, and further maturation of the AI ASIC ecosystem.
The three institutions focused on different areas. UBS Group concentrated on Taiwan Semiconductor's 3DFabric and advanced packaging expansion, raising its forecast for CoWoS capacity to 260,000 wafers per month by the end of 2027. Citi focused on the CPO manufacturing segment, emphasizing active coupling and automated bonding. Nomura turned its attention to testing and equipment, suggesting that post-EIC/PIC bonding testing could become a bottleneck for CPO mass production, and noting that lead times for some equipment have extended to two years.
From an industry trend perspective, advanced packaging is evolving from single-package technologies toward 3D system-level integration, while the core challenge for CPO is shifting from technical validation to scalable manufacturing and testing. As AI chip performance improves, the importance of packaging, optical interconnects, and testing continues to rise, with supply chain capacity expansion extending toward the backend.
Meanwhile, capacity constraints related to equipment and facilities are beginning to emerge, and AI ASICs have become a new growth driver. Overall, the surveys from all three institutions point to the same shift: semiconductor capacity expansion for AI is moving from "front-end production increases" to "full-chain expansion," with packaging, CPO, testing, and equipment expected to become key segments in the next phase.
Taiwan Semiconductor Roadmap: From CoWoS to 3D System Integration
At the exhibition, Taiwan Semiconductor systematically presented its 3DFabric roadmap to address the growth in AI computing power, with advanced packaging and optical interconnects serving as two major pillars.
According to a UBS Group report, Taiwan Semiconductor has achieved mass production of CoWoS with a 5.5x reticle size, achieving yields exceeding 98%. By 2028, it will further expand to a 14x reticle size and support 20-layer HBM stacking, with plans to support 24-layer HBM by 2029.
Panel-level packaging is also accelerating. UBS Group noted that equipment suppliers are gaining confidence in the mass production of Taiwan Semiconductor's CoPoS (310×310mm²). Taiwan Semiconductor aims to complete process and equipment selection by mid-2027 and achieve mass production by 2028.
Notably, Taiwan Semiconductor appears to be adopting a more cautious approach to CoWoS capacity expansion in the second half of 2027, with some CoW outsourcing likely to be handled increasingly by ASE. This indicates that capacity expansion in advanced packaging is spilling over further from Taiwan Semiconductor's internal operations to OSAT manufacturers.
Optical interconnects represent another pathway for Taiwan Semiconductor's 3DFabric to extend toward system-level integration. UBS Group stated that Taiwan Semiconductor's COUPE roadmap aims to achieve 200G/channel by 2026 and increase this to 400G/channel by 2030.
The core contradiction underlying this issue is that the growth in AI computing power is gradually outpacing the improvement in system I/O bandwidth. A speaker from Taiwan Semiconductor pointed out that AI computing demand is growing at a rate of approximately threefold every two years, whereas I/O bandwidth is increasing by only about 1.4 times. As transmission frequencies and distances continue to rise, the limitations of copper interconnects are becoming increasingly pronounced, making optical interconnects a key direction for resolving system-level communication bottlenecks.
CPO Manufacturing: Testing Becomes a Key Bottleneck for Mass Production
As CPO transitions from technical validation to scaled mass production, the challenges facing the supply chain are evolving: the question is no longer just "can it be done," but rather "can it be produced stably and efficiently."
Citi notes that CPO manufacturing involves the integration of multiple components, including EICs, PICs, lenses, and optical fibers/FAUs. Active coupling requires real-time optical power feedback and multi-axis alignment. As the industry moves into large-scale production, further improvements in alignment speed, parallel processing capabilities, and automated bonding levels are required.
Testing has become another major bottleneck. Nomura focuses on Insertion 2, the testing stage after wafer bonding of the EIC and PIC is completed. Due to currently low test throughput, discussions have begun within the supply chain on whether this step can be skipped.
However, Nomura believes that although eliminating Insertion 2 could shorten the production cycle, certain test items cannot be covered by subsequent stages. Therefore, this step remains useful for assessing wafer yield and clarifying supply chain responsibilities. In other words, the trade-off between test efficiency and test coverage is becoming a critical issue that must be addressed for CPO mass production.
UBS Group predicts that the industry may gradually simplify Insertion 2 while increasing reliance on Insertion 3—testing of individual optical engines. At an exhibition, Chroma ATE, a test equipment manufacturer, suggested that CPO testing may shift towards a "shift-to-middle" approach: for high-density scalable switches, a defect in any single optical engine could result in the scrapping of CoWoS-level packaging. Therefore, 100% known-good-die verification at Insertion 3 may become a prerequisite for mass production.
Editor/KOKO